In the art, before an integrated circuit is put into production, the physical layout thereof has to be checked whether it is fit for production. Generally, design-rule violations are checked (such as minimal distance or width requirements on wires) and, more recently, checking is performed whether manufacturing rules are satisfied (manufacturing rules will in general impose a preference for more than minimal distance in addition to the design-rules). Calculating a quality number for the layout, which quality number can be associated to a yield prediction value, can be seen as an advanced way of checking the layout before production: if the quality number is too bad one may opt to modify the design to get better manufacturing yield.
One publication that deals with calculating a yield prediction value is U.S. Pat. No. 6,738,954. In this publication, a quality number calculation is performed on a proposed layout. A number of subdivisions of a circuit are assessed each resulting in an average fault number and a statistical error value of said fault number. Iteratively, a statistical error of the average number is reduced until the statistical error is below an error limit.
U.S. Pat. No. 7,013,441 is another publication that is concerned with calculating a predicted manufacturing yield from an integrated circuit. Here, by selecting library elements from a design database to include in a proposed design for the integrated circuit, a yield is calculated based on a normalization factor that is associated to the library element and used to account for a sensitivity of the library element to a given defect.
U.S. Pat. No. 6,418,551 proposes a design rule checking tool that uses a waiver layout pattern in order to waive a suspected violation of a design rule in a proposed circuit layout. In this way, the number of violations that need assessment can be lowered.
These publications have in common that single quality number statements are given for pass/fail of a certain circuit layout. However, the information of that quality number is not used to propose a modified design.
In U.S. Pat. No. 6,745,372 a layout optimization is provided wherein a system simulates the effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. Accordingly, shapes in a target layout are moved to produce a new target layout that has better process latitude. The patent publication is involved with relaxing a design rule by assessing a change in a target layout. It is not concerned with calculating a quality number.